The present invention relates to improved methods for performing plasma etching for forming a pattern of recessed features in a substrate, e.g., via openings and/or trenches in a dielectric layer overlying a semiconductor substrate comprising at least one active device or region, utilizing an overlying mask including a pattern of openings corresponding to the pattern of features to be formed in the substrate. The present invention enjoys particular utility in semiconductor manufacture wherein ultra-thin metallization pattern masks are employed during reactive plasma etching for forming openings or recesses in a dielectric layer as part of multi-level metallization processing for formation of high integration density, semiconductor integrated circuit (xe2x80x9cICxe2x80x9d) devices having submicron-dimensioned design features.
The escalating requirements for high integration density and performance associated with ultra large-scale (xe2x80x9cULSIxe2x80x9d) integration semiconductor device wiring and interconnection are difficult to satisfy in terms of providing submicron-dimensioned (e.g., 0.18 xcexcm and below, such as 0.15 xcexcm and below), low resistance-capacitance (xe2x80x9cRCxe2x80x9d) time constant metallization patterns, particularly when the submicron-dimensioned features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to micro-miniaturization, and accordingly, responsive changes in interconnection technology are required.
Conventional semiconductor IC devices typically comprise a semiconductor substrate, such as a monocrystalline silicon (Si) wafer including a plurality of active device regions formed thereon or therein, and a plurality of pairs of overlying, sequentially formed inter-layer dielectrics (xe2x80x9cILDxe2x80x9ds) and patterned metal layers. An integrated circuit is formed therefrom containing a plurality of electrically conductive patterns comprising conductive lines separated by interwiring spaces, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of different layers, i.e., upper and lower vertically spaced-apart layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes an electrical contact with an active device region on or in the semiconductor substrate, such as a source or drain region of a transistor. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor IC devices comprising five (5) or more such levels of vertically interconnected metallization are becoming more prevalent as device geometries decrease into the deep submicron range.
A conductive plug filling a via opening is typically formed by a process sequence comprising: (1) depositing an inter-layer dielectric (xe2x80x9cILDxe2x80x9d) on a patterned, electrically conductive layer, e.g., a metal layer comprising at least one metal feature; (2) forming a desired opening in the ILD, as by conventional photolithographic masking and etching techniques, and filling the opening with an electrically conductive material, e.g., tungsten (W); and (3) removing excess conductive material deposited on the surface of the ILD during filling of the opening, as by chemical-mechanical polishing/planarization (xe2x80x9cCMPxe2x80x9d).
One such method for fabricating electrically conductive vias is termed xe2x80x9cdamascenexe2x80x9d type processing and basically involves the formation of an opening in the ILD which is filled with a metal plug. xe2x80x9cDual-damascenexe2x80x9d processing techniques involve formation of an opening in an ILD comprising a lower, contact or via opening section communicating with an upper, trench opening section, followed by filling of both the lower and upper sections of the opening with an electrically conductive material, typically a metal or metallic material, to simultaneously form a conductive (via) plug in electrical contact with a conductive line.
A drawback associated with the use of damascene technology for forming submicron-dimensioned, in-laid metallization patterns and features arises from the loss of the xe2x80x9ccritical dimensionxe2x80x9d (CD) of the mask utilized in the step for forming the recesses in the dielectric layer according to conventional reactive plasma etching process for obtaining the requisite anisotropic etching of the dielectric layer, which loss of CD is attributed to sputter etching of the mask material due to bombardment thereof by ions of the carrier gas/diluent for the reactive plasma etching gas which are generated in the plasma. Loss of CD can pose a significant problem in forming recesses and metallization features according to particular design rules. In addition, the problems associated with loss of CD arising from deleterious sputter etching of the masking material is exacerbated by the requirement for use of ultra-thin layers of masking layers, e.g., from about 300 to about 1,500 xc3x85 thick, when fabricating ULSI devices having feature sizes below about 0.18 xcexcm and with high aspect ratios.
Adverting to FIGS. 1(A)-1(C), shown therein in simplified, cross-sectional schematic form, are views successively illustrating initial, intermediate, and final stages of a conventional reactive plasma etching process for forming submicron-dimensioned recesses in a dielectric layer, utilizing a patterned mask having an initial CD. Referring more particularly to FIG. 1(A), a workpiece 1 is provided in an initial state, comprising a substrate 2, typically of a semiconductor such as a wafer of monocrystalline silicon (Si) or gallium arsenide (GaAs) including at least one active device region or layer formed therein or thereon; a dielectric layer 3, such as an ILD layer, formed on the upper surface of substrate 2 and comprised of one or more inorganic- and/or organic-based dielectric materials, e.g., a low dielectric constant (xe2x80x9clow kxe2x80x9d) material; and a thin, patterned masking layer 4 formed on the upper surface of the dielectric layer 3 and including at least one opening 5 formed therein, as by conventional photolithographic masking and etching techniques, the opening 5 having a critical dimension CD, e.g., for defining the width or diameter of a trench or groove to be formed in the underlying dielectric layer 3. When utilized in the formation of recesses with design features in the submicron range, the thin mask layer 4 preferably is ultra-thin (e.g., from about 300 about 1,500 xc3x85 thick and may be formed of an organic-based photoresist material (e.g., an acetal-type UV-sensitive resin) or an inorganic-based hard mask material (e.g., a silicon nitride).
Referring now to FIG. 1(B), the workpiece 1 including the patterned masking layer 4 is installed within the interior space of a plasma etching chamber and subjected to conventional, anisotropic, reactive plasma etching utilizing a halogen-containing reactive plasma, e.g., a fluorine-containing plasma, for forming a recess 6 in the surface of the dielectric layer 3, the reactive plasma being generated by supplying a gaseous mixture of at least one halogen containing gas (e.g., CCl4, CF4, C4F8, CCl2F2, etc.) as a reactive plasma etching gas, optionally admixed with at least one of oxygen (O2) gas, nitrogen (N2) gas, and hydrogen (H2) gas), and argon (Ar) as an inert carrier gas/diluent for the reactive plasma etching gas, to the plasma etching chamber while maintaining the interior space thereof at a reduced pressure and applying radio frequency (xe2x80x9cRFxe2x80x9d) of microwave (xe2x80x9cxcexcwavexe2x80x9d) electrical power thereto (e.g., at a power of about 1500 W) to generate a reactive plasma therein. FIG. 1(B) illustrates the etch profiles of workpiece 1 approximately half-way through the etching process. As shown therein, portions 4xe2x80x2 (represented by dashed lines in the figure) of the thin masking layer 4 bordering the mask opening 5 have been lost (i.e., consumed) due to sputtering therefrom which is incidental to the reactive etching process and is attributed to bombardment of the masking layer 4 by ions of the inert carrier gas/diluent, i.e., Ar+ ions, generated in the plasma and accelerated towards the surfaces of the workpiece 1. As a consequence of the sputter etching of masking layer 4 and resultant loss (i.e., expansion) of the CD, the sidewalls 6xe2x80x2 of recess 6 have begun to exhibit a slight to moderate amount of inward tapering, i.e., a deviation from perpendicularity with the upper surface of the dielectric layer 3.
At the completion of the etching process, as shown in FIG. 1(C), relatively large portions 4xe2x80x3 of the masking layer 4 (again represented by dashed lines in the figure) have been lost or consumed due to sputtering therefrom and the inward tapering of the recess sidewalls 6xe2x80x2 is quite substantial, resulting in considerable loss in CD, i.e., respective increases to CD+xcex94CD1 and CD+xcex94CD2 at the top and bottom of the recess 6, leading to an undesirable increase in the dimensions of recess 6, particularly at the top, or mouth portion thereof adjacent the upper surface of the dielectric layer 3. Thus, it is apparent that the CD cannot be adequately maintained during recess formation according to conventional reactive plasma etching processing as described above.
As design rules extend further into the submicron range, e.g., about 0.18 xcexcm and below, such as 0.15 xcexcm and below, and the number of metallization levels increases, necessitating a corresponding increase in the requisite number of reactive etching steps for forming recesses such as vias, trenches, grooves, etc., maintenance of the critical feature sizes or dimensions of the metallization/interconnect pattern becomes increasingly important. Accordingly, the problem of increased feature size resulting from undesired coincidental sputtering of the thin masking layer causing loss of the CD during recess formation requires resolution.
Thus there exists a need for reactive plasma methodology enabling the formation of submicron-dimensioned metal vias, contacts, interconnection and routing members, etc., having desired feature sizes with high reliability and performance, and at high product yield. Specifically, there exists a need for methodology for eliminating the problem of loss of CD during formation of submicron-dimensioned recesses which are subsequently filled with an electrically conductive material, e.g., a metal or metal alloy, which methodology is rapid, cost-effective, and avoids the drawbacks and disadvantages associated with conventional reactive plasma etching techniques and provides, inter alia, no or at least a substantially reduced amount of disadvantageous, deleterious physical sputtering of the masking layer.
The present invention, wherein deleterious physical sputtering of a patterned during recess formation by reactive plasma etching is eliminated, or at least substantially reduced, in which: (1) argon (Ar) gas as the inert carrier gas/diluent for the reactive plasma etching gas or gases is replaced with at least one inert carrier gas/diluent having an atomic weight less than that of Ar, such as helium (He) and neon (Ne); and (2) the electrical power supplied to the plasma etching chamber is substantially equal to that supplied to the plasma etching chamber when Ar is utilized, effectively addresses and solves the need for improved methodology for forming submicron-dimensioned recesses in, e.g., dielectric layers, by means of reactive plasma etching, particularly in the manufacture of multi-level metallization semiconductor integrated circuit (IC) devices. Further, the methodology provided by the present invention can be easily implemented in a cost-effective manner utilizing conventional reactive plasma etching apparatus. Finally, the methodology afforded by the instant invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components.
An advantage of the present invention is an improved method for forming at least one recess in a surface of a workpiece by means of reactive plasma etching.
Another advantage of the present invention is an improved method for forming a plurality of submicron-dimensioned recesses in a dielectric layer by means of a reactive plasma etching process which eliminates, or at least substantially reduces, deleterious loss of a critical opening dimension (CD) of an ultra-thin patterned mask utilized for performing the reactive plasma etching process.
Still another advantage of the present invention is an improved method for performing recess pattern formation of a dielectric layer overlying a semiconductor substrate as part of a process for manufacturing a semiconductor integrated circuit (IC) device.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are obtained in part by a method of forming at least one recess in a surface of a workpiece by reactive plasma etching, comprising the steps of:
(a) providing the interior space of a plasma etching chamber with a workpiece including a layer of a masking material on a surface thereof, the layer of masking material comprising at least one opening extending therethrough and having a critical opening dimension (xe2x80x9cCDxe2x80x9d) for exposing a selected portion of the workpiece surface;
(b) supplying the interior space of the plasma etching chamber with a gas mixture comprised of at least one reactive plasma etching gas and a carrier gas/diluent for the at least one reactive plasma etching gas, the carrier gas/diluent comprising at least one inert gas having an atomic weight less than that of argon (Ar); and
(c) forming at least one recess in the workpiece surface by reactive plasma etching utilizing the gas mixture and the layer of masking material for determining the position and dimensions of the at least one recess, the CD of the at least one opening in the layer of masking material remaining substantially constant during the reactive plasma etching, the reactive plasma etching comprising generating within the plasma etching chamber a plasma comprising the at least one reactive plasma etching gas and the carrier gas/diluent by supplying electrical power thereto at a level substantially equal to that supplied to the plasma etching chamber when utilizing Ar gas as a carrier gas/diluent for the at least one reactive plasma etching gas, thereby eliminating, or at least substantially reducing, deleterious sputter etching of the layer of masking material due to bombardment thereof by ions of the carrier gas/diluent during the plasma etching resulting in loss of the CD, relative to when Ar gas is utilized as the carrier gas/diluent.
According to an embodiment of the present invention, step (a) comprises providing a workpiece comprising a semiconductor substrate with a dielectric layer formed thereon, the dielectric layer comprising the workpiece surface, and the layer of masking material comprises a layer of a photoresist or hard mask material; and step (b) comprises supplying the interior space of the plasma etching chamber with a gas mixture comprised of at least one halogen-containing gas as the at least one reactive plasma etching gas and at least one of helium (He) and neon (Ne) gas as the carrier gas/diluent.
In accordance with embodiments of the present invention, step (b) further comprises including at least one of oxygen (O2) gas, nitrogen (N2) gas, and hydrogen (H2) gas in the gas mixture; and step (b) comprises supplying said interior space of the plasma etching chamber with at least a chlorocarbon gas as the at least one reactive plasma etching gas, or step (b) comprises supplying the interior space of the plasma etching chamber with at least a fluorocarbon gas as the at least one reactive plasma etching gas, or step (b) comprises supplying the interior space of the plasma etching chamber with at least a chlorofluorocarbon gas as the at least one reactive plasma etching gas.
According to particular embodiments of the present invention, step (b) comprises providing a workpiece having a dielectric layer thereon formed of a dielectric material selected from oxides, nitrides, and oxynitrides of silicon, or from a low dielectric constant (xe2x80x9clow kxe2x80x9d) material selected from hydrogen silsesquioxane (xe2x80x9cHSQxe2x80x9d)-based materials (e.g.,FOx(trademark) and XLK(trademark)), tetraethyl orthosilicate (xe2x80x9cTEOSxe2x80x9d)-based materials, benzocyclobutene (xe2x80x9cBCBxe2x80x9d), parylene, polyimide, aromatic hydrocarbon-based polymers (e.g., SiLK(trademark)), trimethyl silane based materials (e.g., Black Diamond(trademark)), carbon-doped silicon oxides (e.g. Coral(trademark)), etc.
In accordance with embodiments of the present invention, step (b) comprises providing a workpiece including an ultra-thin layer of masking material having a thickness of from about 300 to about 1,500 xc3x85; and according to particular embodiments, step (b) comprises providing a workpiece wherein the ultra-thin layer of masking material includes a plurality of spaced-apart openings each extending through the layer of masking material to expose a plurality of selected portions of the workpiece surface, each of the openings having a position and CD corresponding to a submicron-dimensioned recess to be formed in the workpiece surface in step (c); and step (c) comprises forming a plurality of high aspect ratio, submicron-dimensioned recesses in the surface of the dielectric layer for use in subsequent formation of vias, interlevel metallization, and/or interconnection routing of at least one active device region or component formed on or within the semiconductor substrate.
According to embodiments of the present invention, step (c) comprises supplying the interior space of the plasma etching chamber with radio frequency (xe2x80x9cRFxe2x80x9d) or microwave (xe2x80x9cxcexcwavexe2x80x9d) electrical power.
According to another aspect of the present invention, a method of manufacturing a semiconductor device comprises the sequential steps of:
(a) providing a workpiece comprising:
(i) a semiconductor substrate including at least one active device region or component formed therein or thereon;
(ii) a layer of a dielectric material overlying the substrate and having a surface; and
(iii) a layer of a masking material overlying the surface of the layer of dielectric material, the layer of masking material comprising at least one opening extending therethrough and having a critical opening dimension (xe2x80x9cCDxe2x80x9d) for exposing a selected portion of the surface of the layer of dielectric material; and
(b) forming at least one recess in the surface of the dielectric layer by a reactive plasma etching process, comprising:
(i) installing the workpiece within the interior space of a plasma etching chamber;
(ii) supplying the interior space of the plasma etching chamber with a gas mixture comprised of at least one reactive plasma etching gas and a carrier gas/diluent for the reactive plasma etching gas, the carrier gas/diluent comprising at least one inert gas having an atomic weight less than that of argon (Ar); and
(iii) reactive plasma etching at least the selected portion of the surface of the dielectric layer exposed through the at least one opening in the layer of masking material, the CD of the at least one opening in the layer of masking material remaining substantially constant during the reactive plasma etching, the reactive plasma etching comprising generating within the plasma etching chamber a plasma comprising the at least one reactive plasma etching gas and the carrier gas/diluent by supplying electrical power thereto at a level substantially equal to that supplied to the plasma etching chamber when utilizing Ar gas as a carrier gas/diluent for the at least one reactive plasma etching gas, thereby eliminating, or at least substantially reducing, deleterious sputter etching of the layer of masking material due to bombardment thereof by ions of the carrier gas/diluent during the plasma etching resulting in loss of the CD, relative to when Ar gas is utilized as the carrier gas/diluent.
According to embodiments of the present invention, step (a) comprises providing a workpiece wherein the semiconductor substrate is comprised of a wafer of monocrystalline silicon (Si) or gallium arsenide (GaAs); the layer of dielectric material is comprised of a dielectric material selected from oxides, nitrides, and oxynitrides of Si or from a low dielectric constant (xe2x80x9clow kxe2x80x9d) material selected from hydrogen silsesquioxane (xe2x80x9cHSQxe2x80x9d)-based materials, tetraethyl orthosilicate (xe2x80x9cTEOSxe2x80x9d)-based materials, benzocyclobutene (xe2x80x9cBCBxe2x80x9d), parylene, polyimide, aromatic hydrocarbon-based polymers, trimethyl silane-based materials, and carbon-doped silicon oxides; and the layer of masking material is comprised of an ultra-thin layer of a photoresist material or hard mask material having a thickness of from about 300 to about 1,500 xc3x85.
In accordance with particular embodiments of the present invention, step (a) further comprises providing a workpiece wherein the ultra-thin layer of masking material includes a plurality of spaced-apart openings each extending through the layer of masking material to expose a plurality of selected portions of the surface of the layer of dielectric material, each of the openings having a position and CD corresponding to a submicron-dimensioned recess to be formed in the surface of the dielectric layer in step (b).
According to further embodiments of the present invention, step (b) comprises forming a plurality of high aspect ratio, submicron-dimensioned recesses in the surface of the dielectric layer for use in forming vias, interlevel metallization, and/or interconnection routing of the at least one active device region or component of the semiconductor substrate.
In accordance with embodiments of the present invention, step (b) comprises supplying the interior space of the plasma etching chamber with a gas mixture comprised of at least one halogen-containing gas as the at least one plasma etching gas and at least one of helium (He) and neon as the carrier gas/diluent; and step (b) further comprises including at least one of oxygen (O2) gas, nitrogen (N2) gas, and hydrogen (H2) in the gas mixture.
Embodiments of the present invention include supplying the interior space of the plasma etching chamber with at least one reactive plasma etching gas selected from the group consisting of chlorocarbon, fluorocarbon, and chlorofluorocarbon gases and supplying the plasma etching chamber with radio frequency (xe2x80x9cRFxe2x80x9d) or microwave (xe2x80x9cxcexcwavexe2x80x9d) electrical power.
Additional advantages and aspects of the present invention will become apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.